Today’s session started with a simulation error in ADS 2023 while working on the AFT05MS004N LDMOS transistor. Every time I tried to run it, I saw the message: “FET2FSL1 is an undefined instance of FET2M.” At first, I wasn’t sure what caused it. After going through the model setup and checking the logs, I found the root of the problem a missing design kit: RF_Power_ADS_DesignKit_ADS2025_3p1. Once I installed the correct version and added it to my workspace using the Design Kit Manager, the issue was resolved and I could move forward.

Instead of jumping straight into advanced simulations, I decided to first check if the MOSFET was behaving as expected. I used the FET curve tracer template in ADS to verify the I-V characteristics. It helped me visualize how the device responded to different biasing conditions. The curves looked good and matched the datasheet behavior, confirming that the model was now set up correctly.

With that confirmed, I moved on to basic DC analysis. I built a schematic where I swept VDS from 0 to 28V and VGS from 0 to 5V to plot the ID vs VDS graph. Then, I fixed VDS at 10V and varied VGS from 0 to 5V to generate the ID vs VGS curve. These plots were helpful in understanding how the transistor behaves under different operating points and the results closely matched the expected performance.

After that, I went ahead with S-parameter simulation. But the initial results were disappointing. The transistor showed extremely poor performance – S21 (gain) was around –45 dB, and S11 and S22 were also very high, indicating serious reflection and mismatch. I realized the transistor wasn’t properly biased. The gate voltage was –2.4 V, which was too negative and likely kept the device in cutoff.

To fix this, I adjusted the bias: VGS = –2.8 V and VDS = 7.5 V. I also added some basic matching and decoupling components: L3 = 58.1 nH, C5 = 69.3 pF, and 1000 pF capacitors. These changes helped stabilize the simulation and ensured the transistor was operating under suitable bias conditions.

The updated simulation gave more consistent results. At 161 MHz, the forward gain (S21) was about –62.3 dB still quite low, but now I knew the transistor was biased correctly. The return losses were still poor, confirming that while biasing was now right, the circuit still needs proper impedance matching to work efficiently.

Next, I plan to focus on designing matching networks to bring the input and output impedances closer to 50 ohms. I’ll use Smith charts, source/load pull techniques, and ADS optimization tools to fine-tune the design. I’ll also re-check the bias point with load-line analysis to ensure it’s operating in the linear region, aiming for a gain closer to 10 dB at 161 MHz.