After completing the stability analysis of the AFT05MS004N transistor yesterday, I focused today on setting up and performing a load-pull simulation using Keysight ADS. The objective was to analyze the transistor’s performance at 161 MHz with a drain voltage of 7.5 V, specifically looking at how output power, gain, and efficiency change with varying load impedances. This is a critical step in RF power amplifier design, as it helps identify the optimal load conditions for maximum performance.

While working on the load-pull simulation, I encountered several challenges. I was initially unsure about the meaning and use of the contour plots generated in ADS. These contours are essential for visualizing performance metrics across a range of load impedances, but without proper understanding, interpreting them was confusing. Additionally, I struggled with reading the values shown in the Dynamic Data Display (DDS). I wasn’t clear on what exactly was being plotted or how to extract key figures such as maximum power or efficiency. These difficulties made it hard to derive useful insights from the simulation output.

To address these issues, I referred back to some instructional content I had been using. One helpful resource was a Youtube videos by Anurag Bhargava to specifically deepen my understanding of load-pull simulations, I turned to the videos given below which clearly explained how the load-pull tuner works in ADS, what the different contours represent, and how to correctly interpret the DDS results.

Thanks to these resources, I was able to refine my load-pull simulation and begin interpreting the results with greater confidence. I now have a clearer understanding of how to use the load tuner block in ADS, how to read the power and gain contours, and how to extract meaningful figures such as Pout, gain, and drain efficiency. This deeper comprehension will be crucial as I move forward in the amplifier design process.

FIG1 : Schematic of Loadpull Analysis of AFT05MS004N

In my simulation, I used the AFT05MS004N transistor model configured for a single-tone load-pull analysis at 161 MHz, with a drain bias of 7.5 V, gate bias of 3.25 V, and an input power level of 15 dBm. The source impedance was set at 50 + j0 Ω, and the load impedances were swept around a fundamental center with harmonic impedances fixed at 1000 Ω for the 2nd and 3rd harmonics. The Smith Chart sweep was defined with a circular region of radius 0.3, centered on 50 + j0 Ω, covering a useful range of load impedances to study amplifier behavior.

Fig. 2 : Simulation Result of Loadpull Analysis of AFT05MS004N

From the Figure 2

Parameter	At Max Power	At Max PAE	At Marker m1	At Marker mPdel_vs_PAE
Load Impedance (Zload)	5.167 + j3.053 Ω	7.231 + j7.019 Ω	12.661 + j10.780 Ω	6.109 + j21.719 Ω
Power Delivered (Pdel)	37.061 dBm	35.713 dBm	34.098 dBm	28.898 dBm
Power Added Efficiency (PAE)	69.779 %	77.953 %	67.952 %	36.420 %
Gain	22.061 dB	13.898 dB	19.098 dB	13.898 dB
Input Impedance (Zin)	–0.062 – j10.216 Ω	–0.334 – j8.962 Ω	–0.693 – j8.359 Ω	0.973 – j7.713 Ω
Bias Current (Ibias)	0.971 A	0.637 A	0.504 A	0.283 A
Reflection Coefficient (ρ, angle)	0.813 / 172.937°	0.752 / 163.689°	0.752 / 163.689°	0.752 / 163.689°

• The maximum power delivered (Pdel) was 37.061 dBm, achieved at a load impedance of 5.167 + j3.053 Ω, with a gain of 22.061 dB and PAE of 69.779%.
• The maximum PAE was 77.953%, achieved at a different load impedance of 7.231 + j7.019 Ω, where the power delivered was 35.713 dBm and the gain was 20.713 dB.
• At the load marked by m1 (12.661 + j10.780 Ω), the PAE was 67.952%, power delivered was 34.098 dBm, and gain was 19.098 dB.
• From the PAE vs Power graph, marker mPdel vs PAE indicated a power output of 28.898 dBm at 36.420% PAE, corresponding to load 6.109 + j21.719 Ω.
• The harmonic source and load impedances were configured at:
  • Fundamental: 50 Ω,
  • 2nd and 3rd harmonics: 1000 Ω,
  • Load Zs at 2nd and 3rd harmonics: 678.4 G – j4.091 T, 1.298 T + j1.416 T.

These results helped visualize the trade-offs between maximum output power and efficiency and guided me toward selecting suitable load conditions for optimal performance.

Contour plots on the Smith Chart clearly illustrated the regions for maximum power (in red) and maximum PAE (in blue), with black dots representing simulated impedance points. The plotted contour levels stepped by 1 dB for gain and 4% for PAE, offering a high-resolution visual of optimal performance regions.

To summarize, today marked the beginning of load-pull simulation in my project workflow. Although I faced initial confusion due to lack of familiarity with the contour plots and DDS interface, I was able to resolve those challenges through focused study and experimentation. The combination of theoretical knowledge and practical simulation is starting to pay off, and I’m now in a better position to optimize the transistor’s performance. Looking ahead, my next steps will involve finalizing the load-pull setup, accurately extracting key performance markers like maximum output power and efficiency, and using those insights to begin the design of the output matching network.